Как перехватывать не нужные сообщения пользователя в бот? Aiogram 3

Z

Znahar

Всем, привет! Как начинающий бото-строитель прошу помощи. Весь диалог пользователя с ботом построен на кнопках ReplyKeyboard, InlineKeyboard. Естественно все кнопки отрабатывают хендлеры @dp.message и @dp.callback_query. А как поймать 'рандомное' сообщение от пользователя и ответить, например, - 'Моя твоя не понимать. Нажми кнопу'. Благодарю за ответ.
 

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мой код выводится на секунду и сразу же закрывается, в чем проблема?

Code: 
pygame.init()
screen = pygame.display.set_mode((600, 300))
pygame.display.set_caption("игра")

myfont = pygame.font.Font('font/BebasNeue-Regular.ttf', 40)
text = myfont.render('PLAY', False, 'White')

run = True
while run:

    screen.blit(text, (300, 100))

    pygame.display.update()

    for event in pygame.event.get():
        if event.type == pygame.QUIT:
            run = False
            pygame.quit() ```
**полужирный**
*курсив*
>цитата

pygame.

cумма попарных произведений не ограниченного количества корней уравнения/чисел (динамический список)

  • Анастасия slaaay
  • Technology
  • Replies: 0
сумма попарных произведений a, b, c = ab + bc + ca

Creating a dynamic trading range

  • Pherdindy
  • Finance
  • Replies: 0
A trading range is determined by price, volume, and time. To accurately represent support and resistance levels, price movements should be weighted by volume. The duration of the trading period is important. If a stock is consistently in a downtrend over a 30-day period, then a trading range doesn't exist. Therefore, the program should dynamically select the appropriate time period for identifying trading ranges. It should also be capable of identifying support and resistance levels even beyond the specified time period, as historical data points may indicate these levels.

This should be done using only OHLC (Open, high, low, close) daily stock quotes with volume data since these are the only ones available to us.

Been thinking about this problem and i'm not sure how to approach the issue for the best support/resistance values. Thought about pivot points, donchian channels, moving averages, VWAP, and etc. But I don't know the best for daily quote data and currently thinking how to make it dynamic. It has to automatically find the right trading ranges for all the stocks. Any leads?

Below is an example of such a trading range that I ideally want to form:

enter image description here

Had one using donchian channels

enter image description here

Also had one version where you just get the minimum and maximum values of a range and get the mean of the price. The purple line is the VWAP calculated by Typical price * Volume traded for the day.

enter image description here

I will run my own tests on the data once I come up with something, but currently most of the options I found don't seem to make too much sense to explain as to why a said support/resistance should be around those areas.

Why `foreach_set()` don't work?

How do I write an integer attribute for each vertex?
For some reason this code doesn't work:

Code: 
import bpy

mh = bpy.data.meshes.new("Mesh")
mh.vertices.add(2)

att = mh.attributes.new(name="a", type='INT', domain='POINT')
att.data.foreach_set('a', [1, 2]) #mh.vertices.foreach_set('a', [1,2])

#AttributeError: foreach_set(..) 'IntAttribute.          data[...]' elements have no attribute 'a'

#>>> bpy.data.meshes['Mesh'].attributes[:]
#[bpy.data.meshes['Mesh'].attributes["a"]]

What am I doing wrong?

Connect\join multiple vertices to one

What i have

I need to make topology tris\quad. So usualy i join verteces one by one to opposite vertex. But in most cases i need to join many verteces to only one or two. Its not hard but it is time consuming. So the question is there an easier way to join them? For example join all selected to last selected or something like this? Some add-on? What i need

Generate 200MHz Phase-Shifted Voltage Sine Waves

  • Hikikomori
  • Physics
  • Replies: 0
I'm looking into a way to construct a circuit that can generate ~200MHz negative voltage sine waves (8 channels), where there is 11 degrees of phase offset between the channels (0 deg, 11 deg, 22 deg, ...). I would like to be able to adjust the frequency, phase offset and possibly amplitude of the individual sine waves/channels.

After browsing different forums, I wasn't able to find anything for my frequency range of interest (50MHz - 300MHz). Some ideas that came to mind after extensive browsing were to use a voltage-controlled-oscillator (VCO), phase-locked loops (PLL), and variable-gain-amplifiers (VGA). Another idea that I thought of was to first generate the desired sine wave and try to use a tapped-delay-line (TDL) to get the phase shifted sines. However, there didn't seem to be any TDLs with small-enough tap-delay-step (not to mention them having a minimum delay of >2ms), which made me give up on that idea.

Do you happen to have any suggestions or recommendations on how I can design such a circuit? Any help is greatly appreciated!!! P.S. the voltage range of interest is [0 ; -10V] (10V P-P centered around -5V)

Initial register value in synthesized design is always 0

  • axk
  • Physics
  • Replies: 0
I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition.

The State register in the below module appears to be 0 initially even if I specify a different default value (I.e. if I set ST_INITIALWAIT to anything but 0 it doesn't work).

I've tried specifying the default value inline with the definition and in an initial block.

Non-zero initial register values work fine in other modules in the same design, so I'm puzzled why it doesn't in this module.

Code: 
module CamSetup(clk, ready, error, scl, sda);
input clk;
output ready, error;
output scl;
inout sda;

parameter ST_READY = 4'd1;
parameter ST_WRITING = 4'd2;
parameter ST_ENDING = 4'd3;
parameter ST_INTERIM = 4'd4;
parameter ST_INITIALWAIT = 4'd0;

parameter REG_COUNT = 1;

//truncated to save space (actually updates 170 registers)
bit [1:REG_COUNT][0:2][7:0] RegValues = {
    8'h42, 8'h7a, 8'h20 
};

parameter CLKS_INIT = 10;
parameter CLKS_INTERIM = 50000;

reg [23:0] InitiCounter = 0;
reg [23:0] InterimCounter = 0;

reg [3:0] State = ST_INITIALWAIT;
reg [7:0] RegIndex  = 0;
reg [2:0] RegByteIndex  = 0;
reg [7:0] WrData = 0;

wire WrDataRq;
wire I2cIdle;
wire Enable = (State == ST_WRITING);
assign ready = (State == ST_READY);


i2c i2c0(.clk(clk), .enable(Enable), .wr_data(WrData), .wr_data_rq(WrDataRq), .idle(I2cIdle), .error(error), .scl(scl), .sda(sda));

always @(posedge clk)
begin

    case(State)

    ST_INITIALWAIT:
    begin
        InitiCounter <= InitiCounter + 1;

        if(InitiCounter >= CLKS_INIT)
        begin
            State <= ST_ENDING;
        end     
    end

    ST_ENDING:
    begin
        if(I2cIdle)
        begin           
            if(RegIndex < REG_COUNT)
            begin
                RegIndex <= RegIndex + 1;
                RegByteIndex <= 0;              
                WrData <= RegValues[RegIndex+1][0];
                State <= ST_INTERIM;
            end
            else
            begin
                State <= ST_READY;
            end         
        end
    end

    ST_INTERIM:
    begin
        InterimCounter <= InterimCounter + 1;

        if(InterimCounter >= CLKS_INTERIM)
        begin
            InterimCounter <= 0;
            State <= ST_WRITING;
        end
    end

    ST_WRITING:
    if(WrDataRq)
    begin       
        if(RegByteIndex < 2)
        begin
            RegByteIndex <= RegByteIndex + 1;
            WrData <= RegValues[RegIndex][RegByteIndex+1];
        end
        else
        begin
            State <= ST_ENDING;
        end
    end         

    endcase

end

endmodule
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